Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache
US9367456B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Nov 22, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.