Storage system and cache control method
US9367469B2 · kind B2 · utility
4Cited by
13References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.