Method and apparatus for designing and generating a stream processor
US9367658B2 · kind B2 · utility
17Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jul 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.