Display apparatus and method thereof
US9368084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2009 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 μs or less. If the delay time of the clock is reduced less than about 2.0 μs, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.