Semiconductor integrated circuit device and system with memory cell array
US9368194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.