Patent · US Active

CMOS inverters and fabrication methods thereof

US9368391B2 · kind B2 · utility

0Cited by

3References

14Claims

0Family size

Assignee

Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

Aimei Lin · Zhangpu, CN
JUILIN LU · Shanghai, CN
Yiqi Wang · Troy, US

Key dates

Filing date	Sep 3, 2014
Grant date	Jun 14, 2016
Priority date	—
Expiry date	Oct 16, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/83138
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.