Semiconductor device with dynamic low voltage triggering mechanism
US9368487B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a depletion inducing structure of a negative dopant type having a gap defined in a bottom portion thereof disposed in the p-well, and a n-channel device disposed in a planar encircled region defined by the depletion inducing structure. The well region is in connection with the substrate through the depletion inducing structure. Upon an ESD stress, the depletion inducing structure induces an expanded depletion region in the substrate under the well region, thus providing a substrate trigger mechanism that reduces the triggering voltage of the ESD protection device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.