Semiconductor memory device
US9368555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Feb 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.