Multi-layer gate dielectric field-effect transistor and manufacturing process thereof

US9368737B2 · kind B2 · utility

Assignee

• Georgia Tech Research Corporation · US

Inventors

• Do Kyung Hwang · Duluth, US
• Jungbae Kim · Seoul, KR
• Canek Fuentes-Hernandez · Atlanta, US
• Bernard Kippelen · Tucson, US

Key dates

• Filing date: Oct 5, 2011
• Grant date: Jun 14, 2016
• Expiry date: Nov 20, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K85/657

Abstract

A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm.