Clock generation circuit, successive comparison A/D converter, and integrated circuit device
US9369137B2 · kind B2 · utility
16Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Oct 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit includes a first loop circuit configured to generate a first clock, and a second loop circuit configured to generate a second clock including a period different from a period of the first clock. A fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.