Circuit arrangement, device and method for 5B/6B coding
US9369148B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Nov 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4908
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for determining and providing a first information I1−, that in a digital input word A B C D E comprising a first input bit A, a second input bit B, a third input bit C, a fourth input bit D and a fifth input bit E, at most only one of the five input bits A, B, C, D, E comprises the value 1 (“high”), a second information I2, that in the input word A B C D E exactly two of the five input bits A, B, C, D, E comprise the value 1 (“high”), a third information I3, that in the input word A B C D E exactly three of the five input bits A, B, C, D, E comprise the value 1 (“high”) and a fourth information I4+, that in the input word A B C D E at least four of the five input bits A, B, C, D, E comprise the value 1 (“high”).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.