Patent · US Active

Distribution of an electronic reference clock signal that includes delay and validity information

US9369225B2 · kind B2 · utility

0Cited by

1References

15Claims

0Family size

Assignee

Intel Deutschland GmbH · DE

Inventors

Markus Hammes · Dinslaken, DE
Christoph Schultz · Essen, DE
Edoardo Valori · Goldkronach, DE
Michael Wilhelm · Lambach, DE
Junlin Yan · Düsseldorf, DE

Key dates

Filing date	Oct 1, 2012
Grant date	Jun 14, 2016
Priority date	—
Expiry date	Sep 17, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH04B2001/0491
WIPO fieldTelecommunications
WIPO sectorElectrical engineering

Abstract

An integrated circuit has a clock subsystem, and a circuit. The clock subsystem is configured to provide a reference clock signal to a first module and a second module. The circuit is configured to distribute information describing characteristics of the reference clock signal to the second module. The information distributed with the circuit enables the second module to adapt the reference clock signal based on the information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.