Circuitry and method for multi-level signals
US9369317B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 27, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Feb 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.