Low package parasitic inductance using a thru-substrate interposer
US9370103B2 · kind B2 · utility
8Cited by
7References
11Claims
0Family size
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Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | May 9, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.