Generating a timeout signal based on a clock counter associated with a data request
US9372500B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 27, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.