Managing a power state of a processor
US9372526B2 · kind B2 · utility
3Cited by
1References
21Claims
0Family size
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Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jun 18, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.