Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
US9372692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2012 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.