Non-disruptive code update of a single processor in a multi-processor computing system
US9372702B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Nov 25, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Updating code of a single processor in a multi-processor system includes commencing of a self-reset of a first processor if a bit is found in a first state, and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.