Compacting trace data generated by emulation processors during emulation of a circuit design
US9372947B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Sep 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.