Page programming sequences and assignment schemes for a memory device
US9373397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Dec 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.