Chip package and method for forming the same
US9373526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Dec 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.