Semiconductor integrated circuit device
US9373611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2012 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.