Transistor assembly as an ESD protection measure
US9373614B2 · kind B2 · utility
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5References
8Claims
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Key dates
| Filing date | Jan 10, 2011 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Feb 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A diode (23) is arranged near a transistor (25) to protect from ESD. The diode comprises a well (5) of a first conductivity type and a doped region (4) of a second conductivity type in opposition to the first conductivity type. The transistor comprises a doped well (2) and a doped region (1) of the first conductivity type. The well (2) of the transistor is doped lower than the well (5) of the diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.