Electrostatic protective device
US9373616B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/815
Abstract
The present invention discloses an electrostatic protective device structure, which comprises a CMOS transistor that is disposed entirely above a P-type silicon substrate and arranged into a multi-finger-pattern structure, wherein on the outermost side on both sides of this electrostatic protective device structure is the source region of the MOS transistor, an active region of other drain region or source region in addition to the outermost source region on both sides is arranged in comb teeth pattern and in pairwise intersection, between the active regions of the adjacent drain region or source region is a field oxide region isolation, and on the drain region or source region is disposed a contact hole connecting metal with the active region, wherein the contact hole on the comb-tooth-pattern and pairwise intersected active region is located at the top of the comb-tooth-pattern active region, i.e. close to a side of the field oxide region isolation far away from the polysilicon gate. The present invention, mainly applied to electrostatic protection of a low-voltage MOS, is capable of not only improving its electrostatic protection capability effectively but also minimizing the oc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.