Semiconductor memory devices and methods of fabricating the same
US9373635B2 · kind B2 · utility
6Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2015 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jul 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.