Sandwich damascene resistor
US9373674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2015 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Mar 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.