Wireline receiver circuitry having collaborative timing recovery
US9374250B1 · kind B1 · utility
111Cited by
1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.