Low-delay buffering model in video coding
US9374585B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2013 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Apr 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/172
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques for low-delay buffering in a video coding process are disclosed. Video decoding techniques may include receiving a first decoded picture buffer (DPB) output delay and a second DPB output delay for a decoded picture, determining, for the decoded picture, a first DPB output time using the first DPB output delay in the case a hypothetical reference decoder (HRD) setting for a video decoder indicates operation at a picture level, and determining, for the decoded picture, a second DPB output time using the second DPB output delay in the case that the HRD setting for the video decoder indicates operation at a sub-picture level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.