Method and apparatus for latency reduction
US9377957B2 · kind B2 · utility
2Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Jun 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an integrated circuit that includes a plurality of input/output (IO) circuits, an instruction receiving circuit and control circuits. The IO circuits are configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit. The instruction receiving circuit is configured to form the instruction from the plurality of bit streams. The control circuits are configured to operate according to the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.