Mechanisms and apparatus for embedded controller reconfigurable inter-processor communications
US9378072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Jul 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reconfigurable inter-processor communications in a controller. The system and method include providing multiple processors in the controller and generating a send buffer and a receive buffer for each of the processors. The system and method further include generating a send table and a receive table for each of the processors where the send table stores identifying information about messages being sent and where the receive table stores identifying information about messages being received, and providing infrastructure services that include protocols for sending and receiving messages between multiple processors in the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.