Memory management unit with prefetch ability
US9378150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2012 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Oct 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.