Voltage level shifted self-clocked write assistance
US9378789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.