Semiconductor memory devices having increased distance between gate electrodes and epitaxial patterns and methods of fabricating the same
US9379134B2 · kind B2 · utility
6Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Oct 6, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Oct 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate. The plurality of interlayer insulating layers and the gate electrodes define a channel hole that vertically penetrates the plurality of interlayer insulating layers and the gate electrodes to expose at least a portion of the substrate. A channel recess is provided in the substrate exposed by the channel hole. An epitaxial pattern fills the channel recess. The epitaxial pattern has an upper surface that is concave and curves inward in a middle portion thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.