Decoupling circuit and semiconductor integrated circuit
US9379707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Dec 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.