Delta-sigma modulator with reduced integrator requirements
US9379732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Requirements placed on the first integrator of a filter in a continuous-time delta-feedback modulator may be reduced by using circuitry to reduce the speed of a signal provided to the first integrator of the modulator. The reduction in speed applied to the signal received at the first integrator may then be compensated with circuitry elsewhere in the modulator, such that the net effect of the slow down and speed up of signals does not affect the output of the modulator. The sigma-delta modulator may be implemented in converters, such as an analog-to-digital converter (ADC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.