Array substrate and manufacturing method thereof
US9383608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate of an LCD includes a substrate, a first wiring layer, a semiconductor film, an insulating layer, a second wiring layer, a passivation layer, a conductive film, and a spacer. The first wiring layer is patterned to a gate line, a gate electrode, and a first laminating layer. The semiconductor film is patterned to a channel layer and a second laminating layer. The second wiring layer is patterned to a source line, a source electrode, a drain electrode, and a third laminating layer. The conductive film is patterned to a pixel electrode and a fourth laminating layer. The spacer is a laminating structure at least includes the first, second, third, fourth laminating layers. A portion of insulating layer overlaps with the first laminating layer, and a portion of passivation layer overlaps with the third laminating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.