Patent · US Active

Integrated circuit with state and data retention

US9383802B1 · kind B1 · utility

2Cited by

6References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Jun Tan · Kepong, MY
Kiun Kiet Jong · Merang, MY

Key dates

Filing date	Jun 20, 2013
Grant date	Jul 5, 2016
Priority date	—
Expiry date	May 9, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/3203
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.