Method and system for reducing thermal load by forced power collapse
US9383804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2011 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jan 19, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t0 to t1. A timer is set to trigger a forced power collapse (“FPC”) that removes all power to the processor from time t1 to time t2. At time t2, the processor may be awakened such that it can resume processing at the full frequency. Advantageously, during the FPC, no leakage power (“PL”) is consumed by the processor between t1 and t2. The result is that the processor averages the same processing efficiency over time t0 to t2 as it otherwise would have if a reduced frequency had been provided to it. However, because no PL was consumed during the FPC, the generation of heat between time t1 and t2 that is related to PL is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.