Method and system for creating a mapping table cache from an interleaved subset of contiguous mapping data for a storage device
US9383927B2 · kind B2 · utility
6Cited by
3References
21Claims
0Family size
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Key dates
| Filing date | May 28, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for handling logical-to-physical mapping in a storage device. The method includes the storage device storing in fast access memory, such as DRAM, only a fixed-size subset of the primary mapping table in non-volatile memory, along with contiguity information of physical addresses for logical address not in the subset that are adjacent to the logical addresses in the subset. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.