Data coherency model and protocol at cluster level
US9383932B2 · kind B2 · utility
10Cited by
1References
26Claims
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Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.