Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
US9384092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.