Patent · US Active

Testing a processor assembly

US9384104B2 · kind B2 · utility

0Cited by

11References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Daniel M. Crowell · Rochester, US
James Stephen Fields, Jr. · Austin, US
Richard B. Finch · New Paltz, US
Harald Pross · Wildberg, DE
Gerald G. Stanquist · Salt Point, US

Key dates

Filing date	Nov 27, 2013
Grant date	Jul 5, 2016
Priority date	—
Expiry date	Sep 6, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/273
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.