System and method for cache entry aging
US9384147B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Nov 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that includes a cache key and a key aging alias in the command buffer. The cache controller includes logic circuitry configured to load the cache command from the command buffer of the first host device into the buffer memory, identify a match, if any, for the cache key in the command queue, perform the cache command, and return cache completion status information to the first host application, wherein the cache completion status information includes a value of the key aging alias in cache metadata when a match for the cache key is found and includes a value of the key aging alias provided by the first host application when a match for the cache key is not found.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.