Configuring routing in mesh networks
US9384165B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2011 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.