Method for reducing input latency on GPU accelerated devices and applications
US9384523B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject technology discloses configurations for receiving, by a first process, a set of input events from an application in which the set of input events includes a set of input update commands. The first process writes the set of input update commands into a low-latency graphics pipeline. The subject technology dispatches, by the first process, the set of input update commands from the low-latency graphics pipeline to a second process. The second process receives the set of input update commands from the low-latency graphics pipeline. The subject technology then writes, by the second process, a set of input data into a shared graphics processing unit (GPU) texture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.