Fully valid-gated read and write for low power array
US9384795B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Apr 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.