Circuits and methods for performance optimization of SRAM memory

US9384826B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Per Torstein Roine · Oslo, NO
• Vinod Menezes · Bengaluru, IN
• Mahesh M. Mehendale · Bengaluru, IN
• Vamsi Gullapalli · Savanuru, IN
• Premkumar Seetharaman · Bengaluru, IN

Key dates

• Filing date: Dec 5, 2014
• Grant date: Jul 5, 2016
• Expiry date: Dec 5, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/412
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.