Data loading circuit and semiconductor memory device comprising same
US9384861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Feb 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.