Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
US9385082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | May 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.