Alignment mark recovery with reduced topography
US9385089B2 · kind B2 · utility
0Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jan 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.